A burn-in process may be used during the final stages in the manufacturing process of integrated circuits (ICs) to reduce the number of failures in the field. Bum-in consists of accelerating common failure modes of an IC by intentionally operating the IC under stress conditions. Burn-in conditions may include, for example, supply voltages, clock frequencies, and temperatures near or in excess of specifications. In this way, ICs which would otherwise fail early in their operating lifetime are detected during testing and discarded, thus improving the reliability of ICs delivered to customers. A burn-in process is desirable whenever the resulting ICs must have high reliability, such as ICs used in supercomputers and high-end servers.
While burn-in is generally advantageous, it also has some drawbacks, due to the fact that the stress conditions may favor other kinds of failures which the burn-in process does not target. For example, a phenomenon known as negative-bias temperature instability (NBTI) occurs when p-channel metal-oxide-semiconductor field-effect transistors (PFETs) are subjected to a negative gate-to-source bias at high temperatures. NBTI is thought to arise from the interaction between hydrogen and holes at the interface between the gate oxide and the semiconductor. Under ordinary conditions, hydrogen atoms passivate interface traps by terminating dangling bonds. NBTI occurs when the interface contains a high hole concentration at high temperature. Under those conditions, holes from the inversion layer break the bond between hydrogen atoms and interface trap precursors and release hydrogen from the interface. The traps, no longer passivated, capture charge at the interface.
NBTI stress affects the circuit performance of the PFET by shifting the threshold voltage (VT) of the device, which in turn affects the drain current of the PFET. Since the propagation delay depends on the PFET drain current, the ultimate effect of NBTI stress is to increase the propagation delay, i.e., to slow down the logic circuit. With time, the delay exceeds a value acceptable for normal operation, and the IC eventually fails. For modern low-voltage ICs, with supply voltages of the order of 1 V, NBTI-induced failure may occur for VT shifts of only a few tens of millivolts.
The threshold voltage shift due to NBTI is asymmetric, because it mostly affects those PFETs that are exposed to a negative gate-source bias. Since the gate-source bias is directly correlated with current flow in a PFET, the amount of NBTI-induced VT shift depends on the amount of time a PFET is in its conductive state, which in turn depends on the particular voltage patterns applied to the IC during the burn-in phase. Not all PFETs in an IC are in a conductive state for the same amount of time, therefore some PFETs suffer a greater VT shift than others.
The VT shift induced by NBTI is not completely irreversible. When the bias and temperature conditions causing the NBTI stress are removed, the PFET may experience a partial recovery to its previous state. The recovery, however, is typically not complete, and depends on the specific bias and temperature conditions applied during the recovery process.
A known solution to removing NBTI is through a high temperature anneal which partially recovers the VT shift caused by NBTI during burn-in. This solution, however, has two main drawbacks. First, the high temperature can cause damage to the IC, and the anneal is complicated to perform once the module has been mounted on a board. Second, the annealing process reduces the NBTI stress on all affected PFETs, not only on those PFETs that were most seriously affected.